In many baseband applications a buffer/amplifier is required which possesses linear operation over an input signal range which extends across the full range of the supply voltage. These buffer/amplifiers are referred to as rail-to-rail-input buffers.
There are two basic types of conventional rail-to-rail-input buffers. In the first type a local high voltage on chip is used to drive a conventional differential input stage. This first type requires a charge pump and a clock signal. A clock signal is not necessarily available in a linear system. Further a clock signal contributes to additional noise.
A second type of rail-to-rail-input buffers use a composite P and N channel differential input pair. Composite N and P channel differential input pairs exist in a number of variants. For maintaining a constant mutual conductance gm the mutual conductance gm is controlled by the switching in and out current sources in the input differential pairs to maintain a constant mutual conductance gm or the input devices are run in a sub-threshold mode where the input currents are switched to obtain a constant mutual conductance gm.
FIG. 1 shows a rail-to-rail-input buffer according to the state of the art. The rail-to-rail buffer as shown in FIG. 1 comprises a differential input having a first input terminal (INN) and a second input terminal (INP) for applying an input signal. The rail-to-rail buffer further comprises a first differential stage DIFFP and a second differential stage DIFFN. The two differential stages are supplied with reference currents I1, I2 respectively. The currents I1, I2 are generated by current sources which are connected to the differential stages. The two differential stages DIFFP and DIFFN are scaled to give the same mutual conductance gm:gmp=gmn=GMfor a given current. The state of the art rail-to-rail-input buffer as shown in FIG. 1 forms part of a circuit which ensures that the common mode voltage at the first input terminal INP and the second input terminal INN is the same, i.e. the INN voltage level tracks the INP input voltage level.
The rail-to-rail buffer according to the state of the art as shown in FIG. 1 has three regions of operation.
In a first middle common mode (CM) operation region both differential pairs DIFFP and DIFFN are contributing and the effective mutual conductance gm summed by the summer is 2×GM.
In a second high common mode (CM) operation region the first current I1 generated by the first common source is reduced to zero when the positive supply voltage VDD is approached. In this high common mode operation region the differential stage DIFFP is switched off and the overall mutual conductance gm is reduced to GM, i.e. only half of the mutual conductance gm in the first middle common mode operation region.
In a third low common mode (CM) operation region of the rail-to-rail buffer according to the state of the art the current I2 generated by the second current source is reduced to zero as the lower supply voltage VSS is approached. In this operation region the differential stage DIFFN is switched off and the overall mutual conductance gm is also reduced to GM, i.e. only half of the mutual conductance gm in the middle operation region. Accordingly the overall forward gain of the rail-to-rail buffer according to the state of the art as shown in FIG. 1 is halved at high in low common mode voltages.
A further disadvantage of the rail-to-rail buffer according to the state of the art as shown in FIG. 1 is that the summer is driven unbalanced in the high common mode operation region and in the low common mode operation region of the rail-to-rail buffer.
To overcome this disadvantage a rail-to-rail buffer has been proposed by U.S. Pat. No. 5,574,401 as shown in FIG. 2. The rail-to-rail buffer according to the state of the art as shown in FIG. 2 comprise additional current mirror circuits (Pmirror and Nmirror) and switching transistors P1, N1. The switching transistors P1, N1, are supplied with reference voltages Vpref and Vnref. The reference voltages set the levels in which the common mode input level switches the circuitry into the high or low operation regions. The rail-to-rail buffer according to the state of the art as shown in FIG. 2 also comprises three regions of operations.
In a first middle common mode (CM) operation region both switching transistors P1 and N1 are off and the rail-to-rail buffer functions exactly as the rail-to-rail buffer shown in FIG. 1. Both differential stages DIFFP and DIFFN are contributing in this operation mode a effective mutual conductance gm which is summed up by the summer of 2×GM.
In a second high common voltage operation region, that is when common mode input voltage on input terminals INP and INN is higher than the reference voltage Vpref supplied to the gate of P1, a current I1 generated by the first current source is redirected through PMOS-transistor P1 and applied to a first current mirror circuit Nmirror. The first current mirror circuit Nmirror multiplies the applied current with a constant multiplying factor, e.g. by a factor 3. The first differential stage DIFFP is switched off when the current I1 is diverted to the Nmirror circuit. The current flowing through the second differential stage is quadrupled by mirroring and multiplying the first reference current I1. When the NMOS-transistor within the second differential stage DIFFN are long channel transistors then the mutual conductance gm is also doubled because the NMOS-transistors are square law devices.
In a third low common mode operation region of the rail-to-rail buffer as shown in FIG. 2, that is when the common mode input voltage supplied to the input terminal INP and INN are lower then the reference voltage VNREF supplied to the gate of the switching transistor N1, the current I2 generated by the second current source is redirected through the NMOS-transistor N1 and the second differential stage DIFFN is switched off. The redirected second reference current I2 is mirrored and multiplied by a second mirror circuit Pmirror by a constant multiplying factor of e.g. three. The currents flowing to the first differential stage DIFFP are then quadrupled. When the PMOS-transistors within the first differential stage are long-channel transistors the mutual conductance is doubled when the PMOS-transistors are square law devices.
The rail-to-rail buffer according to the state of the art as shown in FIG. 2 has as a primary disadvantage that it relies on long-channel devices, e.g. long-channel MOS-transistors within the differential stages DIFFP and DIFFN. The rail-to-rail buffer according to the state of the art can only maintain a constant forward gain when the NMOS-transistors have a square law gm characteristic. When the dimensions of the MOS-transistor within the rail buffer become 100 small a square law current/gm characteristic is no longer fulfilled. Accordingly a rail-to-rail buffer having small dimensions will not provide a constant mutual conductance gm over the full input signal range.
A secondary disadvantage of the rail-to-rail buffer as shown in FIG. 2 is in that the summer is driven unbalanced in the high and low common mode operation regions.
Accordingly it is the object of the present invention to provide a rail-to-rail-input buffer having a constant mutual conductance gm over the full input signal range wherein the geometric dimensions of the integrated elements can be minimised without affecting the mutual conductance.